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Integrated Circuit Systems, Inc.
ICS9248-73
Frequency Timing Generator for Pentium II Systems
General Description
The ICS9248-73 is a single chip clock for Intel Pentium II. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-73 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Features
Generates the following system clocks: - 2 - CPUs @ 2.5V , up to 150MHz. - 1 - IOAPIC @ 2.5V, PCI/2MHz. - 9 - SDRAMs @ 3.3V, up to 150MHz. - 2 - 3V66 @ 3.3V, 2x PCI MHz. - 8 - PCIs @ 3.3V. - 2 - 48MHz, @ 3.3V fixed. - 1 - REF @ 3.3V, 14.318MHz. - 1 - 24_48MHz, @ 3.3V fixed. Supports spread spectrum modulation , down spread 0 to -0.5%, 0.25% center spread. I2C support for power management Efficient power management scheme through PD# Uses external 14.138 MHz crystal

Block Diagram Pin Configuration
48-Pin 300 mil SSOP
*120K ohm pull-up to VDD on indicated inputs. **60K ohm pull-up to VDD on indicated inputs. 1. These pins will have 2x drive strength
Power Groups
GNDREF, VDDREF = REF & Crystal GND3V66, VDD3V66 = 3V66 GNDPCI, VDDPCI = PCICLK GNDCOR, VDDCOR = PLL core GND48, VDD48 = 48MHz GNDSDR, VDDSDR = SDRAM GNDLCPU, VDDLCPU = CPUCLK GNDAPIC, VDDAPIC = IOAPIC
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
Pentium II is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
9248-73 Rev B 2/10/00
ICS9248-73
Pin Descriptions
PIN NUMBER 1 2, 9, 10, 18, 25, 30, 38 3 4 5, 6, 14, 21, 29, 42, 34, 7, 8 11 12 P I N NA M E SEL_3V66 REF0 VDD X1 X2 GND 3V66 (0:1) PCICLK0 FS0 PCICLK1 FS1 PCICLK2 SEL24_48# PCICLK (3:7) PD# SCLK SDATA 48MHz FS3 48MHz 24_48MHz FS2 GND48 SDRAM_F TYPE IN OUT PWR IN OUT PWR OUT OUT IN OUT IN OUT IN OUT IN IN IN OUT IN OUT OUT IN PWR OUT OUT PWR OUT OUT PWR DESCRIPTION This pin selects the 3V66 output frequency. 3.3V, 14.318MHz reference clock output. 3.3V power supply Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 3.3V clock outputs for HUB running at 2XPCI MHz 3.3V PCI clock outputs, with Synchronous CPUCLKS Logic input frequency select bit. Input latched at power on. 3.3V PCI clock outputs, with Synchronous CPUCLKS Logic input frequency select bit. Input latched at power on. 3.3V PCI clock outputs, with Synchronous CPUCLKS Logic input to select output. 3.3V PCI clock outputs, with Synchronous CPUCLKS Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Clock input of I2C input Data input for I2C serial input. 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B Logic input frequency select bit. Input latched at power on. 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B 24 or 48MHz output controlled by SEL24_48#. Logic input frequency select bit. Input latched at power on. Ground for 48MHz outputs 3.3V free running 100MHz SDRAM not affected by I2C 3.3V output running 100MHz. All SDRAM outputs can be turned off t h r o u g h I 2C Ground for 2.5V power supply for CPU & APIC 2 . 5 V H o s t bu s c l o c k o u t p u t , u p t o 1 5 0 M H z d e p e n d i n g o n F S ( 0 : 3 ) pins Refer page 3. 2.5V clock outputs running at PCI/2 MHz. 2.5V power suypply for CPU, IOAPIC
13 15, 16, 17, 19, 20 22 23 24 26 27 28 29 31
41, 40, 39, 37, SDRAM (0:7) 36, 35, 33, 32, 43 45, 44 47 48, 46 GNDL CPUCLK (0:1) IOAPIC VDDL
2
ICS9248-73
Frequency Selection
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU SDRAM PCI MHz MHz MHz 100.23 100.90 105.00 66.89 120.00 124.00 133.30 133.30 140.00 150.00 114.99 70.00 75.00 83.31 90.00 95.00 100.23 100.90 105.00 100.33 120.00 124.00 133.30 133.30 140.00 150.00 114.99 105.00 112.50 124.96 90.00 95.00 33.41 33.63 35.00 33.44 40.00 41.33 44.43 33.32 35.00 37.50 38.33 35.00 37.50 41.65 30.00 31.67 3V66 MHz SEL_3V66=0 66.82 67.26 70.00 66.89 64.00* 64.00* 64.00* 66.65 70.00 64.00* 64.00* 70.00 64.00* 64.00* 60.00 63.33 SEL_3V66=1 66.82 67.26 70.00 66.89 80.00 82.66 88.86 66.65 70.00 75.00 76.66 70.00 75.00 83.31 60.00 63.33 16.70 16.81 17.50 16.72 20.00 20.67 22.21 16.66 17.50 18.75 19.16 17.50 18.75 20.83 15.00 15.83 IOAPIC MHz
Note: * These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.
Clock Enable Configuration
PD # 0 1 CPUCLK LO W ON SD RAM LO W ON IOAPIC LO W ON 66M Hz LO W ON PCICLK LO W ON REF, 48M Hz LO W ON Os c O FF ON VCOs O FF ON
3
ICS9248-73
Byte 0: Functionality and frequency select register (Default=0) (1 = enable, 0 = disable)
Bit Bit 7 0 - 0.25% Center Sperad Spectrum 1-Down Spread Spectrum 0 to -0.5% Bit CPUCLK SDRAM PCICLK (2, 6:4) MH z MHz MHz 0000 0001 0010 0011 0100 0101 Bit (2, 6:4) 0110 0111 1000 1001 1010 1011 1100 1101 1110 100.23 100.90 105.00 66.89 120.00 124.00 133.30 133.30 140.00 150.00 114.99 70.00 75.00 83.31 90.00 100.23 100.90 105.00 100.33 120.00 124.00 133.30 133.30 140.00 150.00 114.99 105.00 112.50 124.96 90.00 33.41 33.63 35.00 33.44 40.00 41.33 44.43 33.32 35.00 37.50 38.33 35.00 37.50 41.65 30.00 3V66 MHz SEL_3V66=0 66.82 67.26 70.00 66.89 64.00* 64.00* 64.00* 66.65 70.00 64.00* 64.00* 70.00 64.00* 64.00* 60.00 SEL_3V66=1 66.82 67.26 70.00 66.89 80.00 82.66 88.86 66.65 70.00 75.00 76.66 70.00 75.00 83.31 60.00 63.33 0 IOAPIC MHz 16.70 16.81 17.50 16.72 20.00 20.67 22.21 16.66 17.50 18.75 19.16 17.50 18.75 20.83 15.00 15.83 0 0 0 XXXX Note 1
Description
PWD
Bit 3 Bit 1 Bit 0
1111 95.00 95.00 31.67 63.33 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2, 6:4 0 - Normal 1 - Spread spectrum enable 0 - Running 1 - Tristate all outputs
Notes: 1. Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are default to 0000. * These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.
4
ICS9248-73
Byte 1: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 28 27 26 31 PWD X X X 1 1 1 0 1 Description FS3# FS0# FS2# 24-48MHz 48MHz 48MHz (Reserved) SDRAM_F
Byte 2: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 32 33 35 36 37 39 40 41
PWD 1 1 1 1 1 1 1 1
Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Byte 3: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 17 16 15 13 12 11 PWD 1 1 1 1 1 Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Byte 4: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 7 8 47 44 45 PWD 0 1 1 X 1 X 1 1 Description (Reserved) 3V66_0 3V66_1 SEL_3V66# IOAPIC FS1# CPUCLK1 CPUCLK0
1
1 1
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
5
ICS9248-73
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time
1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 IDD2.5OP66 IDD2.5OP100 IDD3.3PD Fi CIN CINX TTrans TS TStab tPZH, tPZH tPLZ, tPZH
CONDITIONS
MIN 2 VSS-0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors Select @ 66MHz; Max discrete cap loads Select @ 100MHz; Max discrete cap loads Select @ 66MHz; Max discrete cap loads Select @ 100MHz; Max discrete cap loads CL = 0 pF; PWRDWN# = 0 VDD = 3.3 V Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. Output enable delay (all outputs) Output diable delay (all outputs)
0.1 2.0 -100 300 300 14 21 5
MAX UNITS VDD+0.3 V 0.8 V A 5 A A 380 70 100 10 16 5 45 3 3 3 10 10 mA mA mA MHz pF pF ms ms ms ns ns
12 27
14.318 36 1
Clk Stabilization Delay
1
1 1
Guaranteed by design, not 100% tested in production.
6
ICS9248-73
Electrical Characteristics - CPUCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle
1
SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B
1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V; Freq>= 140MHz VT = 1.25 V; Freq< 140MHz VT = 1.25 V VT = 1.25 V; CPU @ 66.8 MHz VT = 1.25 V; CPU @ 100.23 MHz
MIN 2
19 0.4 0.4 40 43
TYP 2.36 0.33 -34 25 1.5 1.4 48 48 50 500 130
MAX UNITS V 0.4 V -19 mA mA 2 1.8 50 53 175 250 ns ns % % ps ps
tf2B1 d t2B1 tsk2B1 tjcyc-cyc2B1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew
1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tjcyc-cyc1 tjcyc-cyc1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V; 3V66 Freq > 75MHz VT = 1.5 V; 3V66 Freq < 75MHz
MIN 2.4
25 0.5 0.5 45
TYP 3.1 0.18 -55 43 1.55 1.4 48 50 100 350
MAX UNITS V 0.4 V -22 mA mA 2 2 55 175 500 500 ns ns % ps ps ps
Duty Cycle
Jitter, Cycle-to-cycle1 Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
7
ICS9248-73
Electrical Characteristics - IOAPIC
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
SYMBOL VOH4B VOL4B IOH4B IOL4B Tr4B Tf4B Dt4B
tjcyc-cyc4B
CONDITIONS IOH = -8 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
MIN 2
19 0.4 0.4 45
TYP 2.3 0.36 -24 23 1.4 1.45 50
140
MAX UNITS V 0.4 V -16 mA mA 2.1 2.2 55
500
ns ns %
ps
Duty Cycle Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew
1 1
SYMBOL VOH3 VOL3 IOH3 IOL3 Tr3 Tf3
1 1
CONDITIONS IOH = -25 mA IOL = 20 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.25 V
MIN 2.4
41 0.4 0.4 45
TYP 2.9 0.32 -73 50 0.95 1 53 85 110
MAX UNITS V 0.4 V -40 mA mA 2 2 55 250 250 ns ns % ps ps
Dt3 1 Tsk1 tjcyc-cyc3B1
Jitter, Cycle-to-cycle
Guarenteed by design, not 100% tested in production.
8
ICS9248-73
Electrical Characteristics - 48MHz/FS3; REF0
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 dt5 tjcyc-cyc5 tjcyc-cyc5
CONDITIONS IOH = -12 mA IOL = 10 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V, 48MHz/FS3 VT = 1.5 V, REF VT = 1.5 V, 48MHz/FS3 VT = 1.5 V, REF
MIN 2.4
25
TYP 3.1 0.19 -55 42 1.1 1
MAX UNITS V 0.4 V -22 mA mA 4 4 55 55 500 1000 ns ns % % ps ps
Duty Cycle Duty Cycle
45 45
51 52 190 310
Jitter, Cycle-to-cycle Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz; 24_48MHz
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5
tjcyc-cyc5
CONDITIONS IOH = -12 mA IOL = 10 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 2.4
16 1.5 1.5 45
TYP 2.9 0.35 -28 22 2.4 2.2 50
240
MAX UNITS V 0.4 V -20 mA mA 4 4 55
500
ns ns %
ps
Duty Cycle Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
9
ICS9248-73
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs PARAMETER Output High Voltage Output High Voltage Output Low Voltage Output Low Voltage Output High Current Output High Current Output Low Current Output Low Current Rise Time Fall Time
1
SYMBOL VOH1 VOH1 VOL1 VOL1 IOH1 IOH1 IOL1 IOL1 tr1 tf1
1 1
CONDITIONS IOH = -11 mA; Pci0 & Pci1 IOH = -11 mA IOL = 9.4 mA; Pci0 & Pci1 IOL = 9.4 mA VOH = 2.0 V; Pci0 & Pci1 VOH = 2.0 V VOL = 0.8 V; Pci0 & Pci1 VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V; PCI0:1, CL=60pF VOL = 0.4 V, VOH = 2.4 V; PCI2:7 VOH = 2.4 V, VOL = 0.4 V; PCI0:1, CL=60pF VOH = 2.4 V, VOL = 0.4 V; PCI2:7 VT = 1.5 V VT = 1.5 V; CL=60pF for Pci0 & PCI1 VT = 1.5 V; CL=50pF for Pci0 & PCI1 VT = 1.5 V; CL=40pF for Pci0 & PCI1 VT = 1.5 V
MIN 2.4 2.4
25 25 0.5 0.5 0.5 0.5 45
TYP 3.2 3.1 0.12 0.2 -110 -55 82 42 1.5 1.7 1.4 1.7 50 545 360 455 130
MAX UNITS V V 0.4 V 0.4 V -22 mA -22 mA mA mA 2.3 ns 2.3 ns 2 ns 2 ns 55 500 500 % ps ps ps ps
Duty Cycle Skew
1
dt1 tsk1
Jitter, Cycle-to-cycle1
1
tjcyc-cyc1
Guaranteed by design, not 100% tested in production.
10
ICS9248-73
Group Offset Waveforms
Group Skews at common Transition Edges
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) CL = 20 pF for CPU and IOAPIC CL = 50 pF for PCI0 & PCI1, CL = 30 pF for other PCIs, SDRAM and 3V66 GROUP SYMBOL CONDITIONS MIN TYP CPU to SDRAM tCPU-SDRAM VT = 1.5 V; VTL = 1.25 V SDRAM leads CPU by 2.5ns for CPU66 0 100 CPU leads SDRAM by 5.0ns for CPU100 CPU to 3V66 tCPU-3V66 VT = 1.5 V; VTL = 1.25 V CPU leads 3V66 by 7.5ns for CPU66 0 100 CPU leads 3V66 by 0.0ns for CPU100 0 360 IOAPIC to PCI tIOAPIC-PCI VT = 1.5 V; VTL = 1.25 V t3V66-PCI VT = 1.5 V 1.5 2.5 3V66 to PCI Guaranteed by design, not 100% tested in production.
MAX
UNITS
500
ps
500 500 4
ps ps ns
11
ICS9248-73
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
12
ICS9248-73
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
General I2C serial interface information
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 13
ICS9248-73
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS924873 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
14
ICS9248-73
Pin 1 D/2 .093 DIA. PIN (Optional)
Index Area
E/2 PARTING LINE
H L DETAIL "A" TOP VIEW BOTTOM VIEW -eA2 c B A
.004 C
SEE DETAIL "A"
-E-DEND VIEW A1 SEATING PLANE -C-
SIDE VIEW
SYMBOL A A1 A2 B c D E e H h L N
COMMON DIMENSIONS MIN. NOM. MAX. .095 .102 .110 .008 .012 .016 .087 .090 .094 .008 .0135 .005 .010 See Variations .291 .295 .299 0.025 BSC .395 .420 .010 .013 .016 .020 .040 See Variations 0 8
VARIATIONS AC MIN. .620
D NOM. .625
N MAX. .630 48
"For current dimensional specifications, see JEDEC 95."
Dimensions in inches
48 Pin 300 mil SSOP Package Ordering Information
ICS9248yF-73-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
15
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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